In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The Si-based microelectronic technology is currently faced with major materials challenges to achieve further miniaturization of integrated circuit devices. A gate stack containing a SiO2 gate dielectric and a degenerately doped polycrystalline Si gate electrode, which has served the industry for several decades, will be replaced with a gate stack having a higher capacitance.
For example, high-capacitance dielectric materials may be used to replace conventional SiO2 gate dielectric materials. Such high capacitance dielectric materials, known as high-k materials (where “k” refers to the dielectric constant of the material), feature a dielectric constant greater than that of SiO2 (k˜3.9). In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrates (e.g., SiO2, SiOxNy). High-k materials may, for example, incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO (k˜5−25), and HfO2 (k˜25)).
In addition to the gate dielectric layer, the gate electrode layer also represents a major challenge for future scaling of microelectronic devices. The introduction of metal-containing gate electrodes to replace the traditional doped poly-Si gate electrode can bring about several advantages. These advantages include elimination of the poly-Si gate depletion effect, reduction in sheet resistance, better reliability and potentially better thermal stability on the advanced high-k dielectric materials. In one example, switching from poly-Si to a metal-containing gate electrode can achieve a 2-3 Angstrom (Å) improvement in the effective or electrical thickness of the gate stack. This improvement occurs largely because the problem of poly-Si depletion at the interfaces with other materials is removed entirely.
Workfunction, resistivity, and compatibility with complementary metal oxide semiconductor (CMOS) technology are key parameters for the new gate electrode materials. The workfunction of a material is the energy required for an electron to move from the Fermi level of a material into free space. One of the material selection criteria for the metal-containing gate electrode is that the workfunction be tunable. Positive-channel Metal Oxide Semiconductor (PMOS) and the Negative-channel Metal Oxide Semiconductor (NMOS) transistor gate electrodes require different gate materials be used in order to achieve acceptable threshold voltages; the former having a Fermi level near the silicon valence band (E˜4 eV), and the latter having a Fermi level near the conduction band (E˜5.1 eV). TABLE 1 shows the workfunction for low, midgap, and high work function metals and metal-containing materials.
TABLE 1METALWORKFUNCTION (eV)Al4.3Ti4.33V4.3Cr4.5Mn4.1Fe4.7Co5Ni5.15Nb4.3Mo4.6Ru4.7Rh4.98Hf3.9Ta4.25W4.55Re4.96Os4.83Ir5.27Au5.1TaN/TaSiN3.9-4.3
Several metal gate electrodes have been studied as a replacement for poly-Si, including Re, W, Mo, Ta, Ti, TaN, TiN and TaSiN. The metal gates must have suitable work function and required thermal and chemical stability with underlying thin gate dielectrics for gate-first CMOS processing, including high-k dielectrics such as HfO2, ZrO2 and their silicates. However, midgap work function metal gates are subjected to a serious problem in that the threshold voltage for the metal gate metal oxide semiconductor field emission transistor (MOSFET) is larger than that for poly-silicon gate transistor. Consequently, buried channel technology is necessary to reduce the threshold voltage of metal gate MOSFETs and that results in degradation of device characteristics including threshold voltage deviation, drive current, etc. Threshold voltage deviation becomes a more serious problem in the sub-100 nm regime because the threshold deviation is an obstacle to realize low voltage and lower power operation.
While metal gate electrode layers do not need to be doped to be electrically conductive, there is not one metal that can set the work function, the energy required to pull an electron free from the surface of the electrode, for both NMOS and PMOS devices. To replace n+ and p+ poly-Si and maintain scaled performance, it is necessary to identify pairs of metals or metal-containing materials with work functions that are close to the conduction and valence edges of Si. Mid-gap work function metals and metal-containing materials (e.g., TiN and W) are inadequate for advanced bulk-Si CMOS devices due to large low-voltage operation threshold voltages and severely degraded short channel characteristics. Control over the gate electrode workfunction can be achieved by depositing a composite metal-containing gate electrode layer, where composition of the layer can be adjusted to obtain the desired workfunction of the gate electrode.
The interactions of different materials at layer interfaces in a gate stack can affect the workfunction and other properties of the gate stack. The measured workfunction of a gate stack depends upon bulk and surface material properties, crystallographic orientation, and the permittivity of the dielectric layer interfacing with the gate electrode layer. High-energy implantation of dopant ions (e.g., nitrogen ions) into a metal gate electrode layer overlying a dielectric layer in a gate stack has been previously researched in order to lower the workfunction. However, ion implantation methods that include exposing the metal layer to high-energy ions can damage the gate stack, for example cause charging damage of the dielectric layer that can increase the leakage current and the reliability of the dielectric layer. The charging damage from exposure of high-energy ions is expected to increase as the minimum feature sizes get smaller and the different materials layers that form gate stacks get thinner. Therefore, new methods are needed for processing gate stacks and, in particular, new methods for tuning the workfunction of the gate stacks.